Processor Architecture Viva Question Answer

Q.2 List and briefly define the possible states of an instruction execution.

Ans: Processor execute instructions in multiple stages, those possible stages are as following but it can be little bit different architecture by architecture however basic idea is same

Instruction address calculation (IAC): Determine the address of the next instruction to be executed.

Instruction fetch (IF): Read instruction from its memory location into the processor.

Instruction operation decoding (IOD): Analyze instruction to determine type of operation to be performed and operand(s) to be used.

Operand address calculation (OAC): If the operation involves reference to an operand in memory or available via I/O, then determine the address of the operand.

Operand fetch (OF): Fetch the operand from memory or read it in from I/O.

Data operation (DO): Perform the operation indicated in the instruction.

Operand store (OS): Write the result into memory or out to I/O.

Q.3 What is interrupts?

Ans: A signal informing a program that an event has occurred. When a program receives an interrupt signal, it takes a specified action (which can be to ignore the signal). Interrupt signals can cause a program to suspend itself temporarily to service the interrupt.

Q.4 What are sources of interrupts?

Ans: Interrupt signals can come from a variety of sources such as internal or external. Interrupts can also be generated by other devices, such as a scanner or printer, to indicate that some event has occurred. These are called hardware interrupts. Interrupt signals initiated by programs are called software interrupts. A software interrupt is also called a trap or an exception

Q.5 List and briefly define two approaches to dealing with multiple interrupts.

Ans: (1) Disable all interrupts while an interrupt is being processed.
(2) Define priorities for interrupts and to allow an interrupt of higher priority to cause a lower-priority interrupt handler to be interrupted.

Q.6 What types of transfers computer’s interconnection structure (e.g., bus) support?

Ans: Memory to processor: The processor reads an instruction or a unit of data from memory.

Processor to memory: The processor writes a unit of data to memory.

I/O to processor: The processor reads data from an I/O device via an I/O module.

Processor to I/O: The processor sends data to the I/O device.

I/O to or from memory: For these two cases, an I/O module is allowed to exchange data directly with memory, without going through the processor, using direct memory access (DMA).

Q.7 What is the benefit of using a multiple-bus architecture compared to a single-bus architecture?

Ans: With multiple buses, there are fewer devices per bus. This (1) reduces propagation delay, because each bus can be shorter, and (2) reduces bottleneck effects.

Q.8 List and briefly define the functional groups of signal lines for PCI.

Ans: System pins:

Include the clock and reset pins. Address and data pins: Include 32 lines that are time multiplexed for addresses and data. Interface control pins: Control the timing of transactions and provide coordination among initiators and targets. Arbitration pins: Unlike the other PCI signal lines, these are not shared lines. Rather, each PCI master has its own pair of arbitration lines that connect it directly to the PCI bus arbiter. Error

Reporting pins:

Used to report parity and other errors. Interrupt Pins: These are provided for PCI devices that must generate requests for service. Cache support pins: These pins are needed to support a memory on PCI that can be cached in the processor or another device. 64-bit Bus extension pins: Include 32 lines that are time multiplexed for addresses and data and that are combined with the mandatory address/data lines to form a 64-bit address/data bus. JTAG/Boundary Scan Pins: These signal lines support testing procedures defined in IEEE Standard 1149.1.